1. Technical Field
The present invention relates to semiconductor devices and, more particularly, to a semiconductor device in which a semiconductor chip has a central area on which pads are disposed and connected to terminals of a package.
2. Related Art
In recent years, attempts have heretofore been made to achieve the speeding up and large-scale integration of a semiconductor device while promoting the miniaturization of a package for downsizing the device. For a large-capacity storage device, a dynamic access memory (hereinafter abbreviated to DRAM) has been developed with a storage capacity in a gigabit class and mounted on a package in a small size. For the miniaturization of the package, a technology has been implemented to provide a ball grid array (hereinafter abbreviated to BGA) of a surface mount type in which solder balls are placed on a package substrate. The placement and related electrical function of the solder balls of the BGA package are standardized and normalized. Such standardization is realized on a DRAM of a dual DOUBLE data rate 2 (DDR2) mode that is determined under JEDEC (Joint Electron Device Engineering Council) in which the placement of the solder balls for the substrate is specified.
Even with the DRAM having the same size in memory capacity, the DRAM includes various models with various numbers of bits for data to be simultaneously input and output. The DRAM is classified into a 4-bit component, an 8-bit component, a 16-bit component, 32-bit component and a 64-bit component etc., in terms of I/O width. Pin layouts of the components with such different number of bits are arranged to have a commonality to enable a user to achieve expansion or reduction of a storage capacity in a simplified fashion. That is, the commonality and standardization of the pin layouts in BGA of the components with various bits ensure an ease of expansion and reduction of such a storage capacity.
When semiconductor manufacturers conduct developments of the 4-, 8-, 16-, 32- and 64-bit components into commercialization, various techniques have been adopted as described below with a view to increasing development efficiency. These components have been developed as family products with a commonality. These components are handled as the same products on a chip production line and product change is made through bonding options. Or, product change is performed on a chip fabrication step through aluminum master slicing technique.
Further, a data pad layout of a semiconductor chip is arranged to have versatility with expansion capability. The other technique includes an effort to allow a layout of chip data pads to correspond to a standardized layout of BGA solder balls.
For the standardization of the layout for the solder balls (pins), not only the data pins (terminals) but also various pins (terminals) for a data power source and ground are specified and various pins (terminals) for data (DQ), a data power source (VDDQ) and data ground (VSSQ) are specified in one group. When handling data of multiple bits, the semiconductor chip includes, in addition to pins for the power source (VDD) and data ground (VSS) for a circuit in general, pins for the data power source (VDDQ) and data ground (VSSQ). This is because locating the pins for the data power source (VDDQ) and data ground (VSSQ) achieves the suppression of power and ground noises, caused by simultaneous operations in a data circuit, and enables high-speed data transmission.
The pin layouts (each with a ratio between the numbers of terminals) for data (DQ), the data power source (VDDQ) and data ground (VSSQ) are grouped in layouts of DQ:VDDQ:VSSQ=1:1:1 for a 4-bit component and DQ:VDDQ:VSSQ=2:1:1 for a component of more than 8 bits. A multiple-bit component with the number of bits greater than 8 bits includes a structure composed of repeatedly placed basic structures of the 8-bit components. To be ideal, the multiple-bit component with the number of bits greater than 8 bits may preferably have a ratio of DQ:VDDQ:VSSQ=1:1:1. However, due to restriction of the number of pads on the semiconductor chip, that ratio is specified as 2:1:1. Therefore, for the multiple-bit component, consideration needs to be taken on a pad layout of a data family that can suppress power and ground noises.
FIG. 6 is a pad layout view illustrating a pad layout 2 for a data family of such a semiconductor chip of the related art. Here, symbols “DQ”, “VDDQ” and “VSSQ” designating data, the data power source and data ground will also be used for solder balls (pins) and lands of the package, and for pads and lead wires of the semiconductor chip unless no particular confusion is caused.
In FIG. 6, pads 1 are placed in a central area of the semiconductor chip along a single row. This layout represents an 8-bit component that includes one unit having respective pads for data ground (VSSQ), two data (DQ) and the data power source (VDDQ) in sequence and another unit having respective pads placed for the data power source (VDDQ), two data (DQ) and data ground (VSSQ) in sequence. The former unit is reversed in pad layout with respect to the latter unit. These units are repeatedly placed forming the 8-bit component. The 8-bit component has the pads for data, data power source/ground with the number of pads being specified in a ratio of DQ:VDDQ:VSSQ=2:1:1.
The pads placed in the chip center are alternately bonded via wires 4 to solder ball lands (not shown) located up and down each for one unit in upper and lower directions. Solder balls (not shown) are fixedly secured onto the lands. Since adjacent pads for data power sources (VDDQ) of the units are independently wire bonded in the upper and lower areas, no issue has occurred in inductance of the lead wires of the data power sources (VDDQ).
More particularly, abbreviating data ground (VSSQ) to “G”, data (DQ) to “S” and data power source (VDDQ) to “V”, the unit layouts can be expressed as G-S-S-V and V-S-S-G, respectively. In FIG. 6, the pads are placed in one row and the unit in layout of G-S-S-V is wire bonded to the solder ball lands on the upper side while the unit in layout of V-S-S-G is wire bonded to the solder ball lands on the lower side. Accordingly, even if the data power source pads are consecutively placed, the lead wires extend from the respective pads in the upper and lower areas in opposite directions and play a role as two power source pads.
However, applying the pad layout of the related art to DRAM with further high-capacity results in new issues. With the chip in which the pads are placed in the chip center along the single row and memory cell arrays are located up and down, issues have occurred in that the chip size becomes too long in a lateral direction as shown in FIG. 7A and a shortage occurs in a photoresist exposure area on a production stage.
As shown in FIG. 7B, the present inventors have conducted studies on a scheme in that the memory cell arrays are located on both sides of the pad area and the two rows of pad layouts are placed in the pad area of the central portion. However, under situations where the related art pad layouts include data ground (VSSQ), two data (DQ) and the data power source (VDDQ) and are placed in the two rows, an undesirable consequence has turned out in that inductance causes disturbance in waveforms with the resultant inability of satisfying data transmission speed characteristic that is speeded up.
FIG. 8 is a layout view showing a pad layout and a standardized land (or ball) layout together with wirings. In the Figure, the same pad layout as that described with reference to FIG. 6 is applied to each layout of a chip with 8-bit structure having two rows of pad layouts. In FIG. 8, the pad layout is shown including a unit (unit of G-S-S-V) having pads for data ground (VSSQ), two data (DQ) and a data power source (VDDQ) placed in sequence and the other unit (unit of V-S-S-G) having pads for the data power source (VDDQ), two data (DQ) and data ground (VSSQ) placed in sequence with these neighboring units being placed up and down in two rows.
Therefore, with areas where adjacent pads are consecutively placed like V-V, G-G, lead wires extend from these pads in the same direction. Since two pads are juxtaposed to each other for the data power source (VDDQ) but are collected in a single line in the vicinity of the pads, the number of data (DQ) sharing the single lead wire for the data power source (VDDQ) includes four pieces equal to a value two times that of the related art. In FIG. 8, arrows designate that the four pieces of data lead wires share a single data power source lead wire. Thus, the data power source lead wiring has an adverse effect and has inductance which is equivalently doubled compared with that of the related art structure shown in FIG. 6. Such a condition similarly applies to a structure wherein the unit of V-S-S-G and the unit of G-S-S-V are placed adjacent to each other in this sequence. This is because such a structure has a consecutive area like a layout of G-G.
For a measure to address such issues, independent lead wires are conceivably placed for the respective pads of the data power sources and connected to solder ball lands for two data power sources. In such a case, due to electric current flowing through the independent lead wires in the same direction, a sum (effective inductance) of mutual inductance and self-inductances of the independent lead wires increase. (Also, if electric current flows in opposite directions, mutual inductance acts in reversed subtraction in contrast to the situation mentioned above.) Such an increase in inductance of the power source lead wire and ground lead wire causes an increase in power and ground noises, degradation in quality of an output signal on data (DQ) and degradations in a voltage margin of a device and a timing margin while causing negative impact on high frequency characteristic of the device during simultaneous switching when data is outputted.
With a 4-bit component shown in FIG. 9, the same semiconductor chips as those of the 8-bit component are employed in general practice. Data power source pads and ground pads are wire bonded and parts of data pads are not wire bonded with only pads corresponding to 4 bits being wire bonded. This allows an 8-pad structure in layouts of G-S-S-V, V-S-S-G of an 8-bit structure to be formed in a 6-pad structure in layouts of G-S-V, V-S-G. While the related art structure took the ratio of DQ:VDDQ;VSSQ=1:1:1, the number of data (DQ) sharing a single lead wire for the data power source (VDDQ) results in two pieces that are equal to a value two times that of the related art structure. Even with the 4-bit component, the same issues as those of the 8-bit component arise with the resultant occurrence of a factor causing deterioration in high frequency characteristic of the semiconductor device.
In such a way, it has turned out by the present inventors that both the 4-bit and 8-bit components have further deteriorated characteristics than those of currently available products and are not suited for high-speed data transmission. Thus, new task has been arising to provide a pad layout of a data family that complies with a solder ball layout specified under standardization while providing versatility for application to a multiple-bit component and suitability for the future of further high-speed data transmission.
A pad layout for a chip mounted on a BGA package is disclosed in Japanese Unexamined Patent Application Publication No. 2001-185576. This publication discloses the BGA package in which chip pads disposed in a central area of the chip are wire bonded to substrate pads located on both sides of the BGA substrate. A technology is disclosed wherein the substrate pads located on one side of the BGA substrate are disposed in the order of pads for a power source potential, a signal line and a ground potential to allow reduction in mutual inductance in wirings.
However, with the structure disclosed in the above patent publication, the chip pads are placed in a central area of the chip along a single row in layout of a power source, ground and a signal line with a ratio of 1:1:1. Accordingly, this patent publication has no problem recognition related to a two-row pad layout that is a task of the present invention to be addressed and provides no solution to the task of the present invention with the issues mentioned above remaining unaddressed.
As set forth above, with the semiconductor device formed in a large-scale integration and increased storage capacity, pad layouts need to be placed in two rows along a central area of the semiconductor chip. An urgent issue arises to find a solution to a pad layout of a data family that includes two rows of pad layouts in association with a layout of the solder ball lands (pins) determined as a standard and has versatility coped with a multiple-bit component to enable high-speed transmission.